TAG 300 Level EIE

But Dr.Owoleni probably would

The assignment on BCD 7 bit with karnaugh map and logic gates He did not set it as a question

This is just for Engr.Gabriel's part Dr. Olowoleni and Omoruyi will still set questions based on their parts Go through our test questions

EIE 327 AOC 1. FLIP FLOPS 2. EXPLANATION OF 4 BIT PARALLEL ADDER a. Draw full block diagram b.Why can you use a half adder for the least bit? 3. EXPLAIN FULLY a. A NAND latch b. A NOR LATCH Using S, R inputs and in QA form it should have the truth table too, and a diagram 4. SUBTRACTOR AND ADDER a. Practice the 3-bit truth table he gave us in class; The table for adder is with sum and carry, while the table for subtractor is with borrow and difference NB: You can use 2 half adders to generate this, learn how 5. FREQUENCY DIVISION AND COUNTER NB: MAKE SURE YOU ADHERE TO THE RISING AND FALLING EDGE SIGNS 6. 1 shot: We calculated pulse width in class. a. It might be retrievable or non-retrievable so learn both b. Draw the diagram with external and internal resistors, capacitors etc

Hi guys, if you've solved any PQ or test question and want us to post it you can send them to @mistieeee, @tireni or @domini0n_o, it would really be appreciated ❤️

Hi guys, if you've solved any PQ or test question and would like to help others you can them send to @mistieeee, @tireni or @domini0n_o, it would really be appreciated ❤️

#EIE323_PQ

#EIE321_note

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