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IBM Hiring Fresher Software Application Developer Cloud FullStack https://www.way2fresher.com/job/ibm-hiring-fresher-software-application-developer-cloud/

IB-ACIO-Recruitment-2023-Notification_231125_005336.pdf6.91 MB

DOC-20231022-WA0006_231022_163406.pdf3.31 KB

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Job openings at CEET, IIT Madras We are hiring fresh energetic graduate Engineers for a Project on Speech Recognition, Analytics, NLP and BOT at CEET, IIT Madras. We are looking for people who are quick learners, self-motivated and have strong aspirations to grow. Position: Project Associate (Speech Recognition) No of candidates : 6 Qualification: B.E/B.TECH (ECE/EEE/CSE with 65 % or 6.5 CGPA and above) Salary : ₹ 3.6 lacs per annum Location : Chennai Joining : Immediate Required skill : Programming (preferably python) Knowledge in Linear algebra, Probability Basic knowledge in Data Structures, Digital Signal Processing Desirable skill : Some Knowledge in Natural Language Processing and Deep Learning. Interested applicants will also have the opportunity to pursue MS at IIT Madras alongside employment. If this role interests you, mail across your profile immediately to hr@tenet.res.in with subject line - Application for Project Associate (Speech Recognition)

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Dear Students, A huge opportunity, We are pleased to inform you that Edveon Technologies Private Limited, is hiring candidates. Job Role: Chip Verification Engineer Experience: 0 to 5 years Salary: 4LPA to 6LPA No. of Positions – 20 nos Qualification: U.G - B.E/ B. Tech - ECE, EEE, CSE, IT - Upto 2022 Passouts P.G - M.E / M.TECH VLSI, Embedded, Power Electronics, Applied Electronics, etc - Upto 2024 Passouts Work Location: Chennai Food and Accommodation are Free for 3 months during the training period. Roles and Responsibilities: • To play the role of Verification engineer at the Block level, Chip level Functional verification. • Develop verification test plans from design specifications • Development of test environments using System Verilog and UVM verification methodologies. • Create multiple test cases as per the test plan and launch regressions. • Generate Code/Functional coverage, analyze coverage results, and correlate with the test plan. • Working with the design team members to identify and quickly resolve problems with the design. • Communicate regularly with the team members to resolve issues and report status. • Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges. Interested candidates can attend the direct interview. Date: 26th August, Saturday Time: 10.00 AM location link - Chennai, Siruseri https://goo.gl/maps/2BPgCkG2rxh75n1j6 Hereby, attaching the aptitude test study links for your reference. Kindly refer to it for your interview process. Aptitude : • https://www.indiabix.com/logical-reasoning/questions-and-answers/ • https://www.indiabix.com/aptitude/questions-and-answers/ • https://www.indiabix.com/logical-reasoning/statement-and-assumption/ Digital : • https://www.javatpoint.com/digital-electronics Programming : • https://www.w3schools.com/CPP/cpp_oop.asp

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