Avid basamad nasr Co.,Ltd

𝕍𝕠𝕝𝕦𝕞𝕖 𝟟𝟜, ℕ𝕦𝕞𝕓𝕖𝕣 𝟟, 𝕁𝕦𝕝. 𝟚𝟘𝟚𝟞 

📂 Papers

𝕍𝕠𝕝𝕦𝕞𝕖 𝟞, ℕ𝕦𝕞𝕓𝕖𝕣 𝟜, 𝕁𝕦𝕝𝕪 𝟚𝟘𝟚𝟞 

📂 Invited and Regular Papers

Regular Papers • Sub-Terahertz Wideband ASK Transceiver for 14/27/64 Gb/s 0.27-km/0.12-m/0.1-mm Interconnection in 28-nm CMOS • A K/Ka-Band Transmit/Receive Front-End With Triple-Coupled Transformer Technique in 65-nm Bulk CMOS • A 10–72 GHz SDR Receiver With Compact and Low-Phase-Noise LO Frequency Quintupler • A 19-dBm 110–142-GHz CMOS Power Amplifier With Device-Centric Power Boosting and Dual-Coupled Slotline Combiner • A 300-GHz-Band 16.2-dBm EIRP Four-Element Amplifier-Last Phased-Array Transmitter With On-Chip Vivaldi Antenna in 65-nm CMOS • A High-Power Wideband Sub-THz Power Amplifier With Asymmetric Slotline-Based Series–Parallel Combiner in 130-nm SiGe BiCMOS Technology • Theoretical Analysis and Design of a 22–44-GHz Quasi-Balanced Doherty Power Amplifier With Enhanced Wideband PAE Performance and 3:1 VSWR Tolerance in 28-nm FD-SOI CMOS • A Compact, Wideband Complex Cascode Power Amplifier With LC Neutralization for VSWR-Resilient Operation in High-Density Phased Arrays • A Dual-Band Reconfigurable Filtering Power Amplifier for 5G mmWave Applications • A 2–18 GHz High-Efficiency CMOS Nonuniform Distributed Power Amplifier With a Novel Reconfigurable Inductive Termination • Design and Analysis of a 13.7–41 GHz Ultra-Wideband Frequency Doubler With Cross-Coupled Push-Push Structure • Adaptive Linearity Enhancement of Low-Noise Amplifiers Using Doherty Active Load Modulation • A 4.21-to-15.18 GHz Magnetically Reconfigurable and Fully Symmetrical Quad-Core Quad-Mode VCO • A Compact Reconfigurable Dual-Path Dual-Band LNA for 5G NR FR2 Applications • A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique • A 23.4–42.1-GHz Fractional-N Synthesizer With ADC-Based Direct Phase Digitization • A Pseudo-Series Resonance CMOS Oscillator • A 433-MHz Wireless Power and Data Transfer System for Smart Contact Lens With Integrating Receiver Achieving 0.02% Modulation Index • A Dual-Band Simultaneous RF Energy Harvesting System With Globally Optimized 3-D MPPT and Efficiency Enhancement • 25-Gb/s 850-nm Monolithic Optical Receiver With a Si APD Bias Controller Using Histogram Monitoring • A SPAD Flash LiDAR Sensor With Push-Pull Analog Counter Achieving a 0.12% Depth Precision at a 70 m Depth Range • A 65-nm CMOS Machine-Learning-Enhanced Bandwidth-Efficient LiDAR • A 200-MHz-BW Time-Interleaved Pipelined-SAR ADC With Shared Residue Integrator • A 136.6-dB-DR 174.3-dB-FoMs Versatile Current-to-Digital Converter With a Truncated-Noise-Shaped Baseline-Servo-Loop • A 0.5–2.5-GS/s Resettable Ring-VCO-Based ADC Eliminating Quantization-Noise Shaping • A 12-bit 1-GS/s Current-Steering DAC With Paired Current Source Switching Background Mismatch Calibration • Xiling: Cryo-CMOS Manipulator Using Dual 18-bit R-2R DACs for Single-Electron Transistor at 60 mK • A Noise-Shaping SAR-Based ExG Sensing Frontend With Dynamic Input-Impedance Boosting and Prediction-Assisted Mismatch-Shaping DEM • A Noise-Reconfigurable TDM-Based Chopper-Stabilized ECG Amplifier With 142.8-GΩ Input Impedance • A 94.8-nW Battery-Free Intelligent Silicon Platform for Distributed Multimodal Sensing With Adaptive and Event-Driven Computing • ANP-O: A 67 μW/Channel, 0.13 nW/Synapse/Bit Nose-on-a-Chip for Noninvasive Diagnosis of Diseases With On-Chip Incremental Learning • A 350-pW Implantable Ventricular Arrhythmia Detection Engine With Bayesian Uncertainty Quantification in 65-nm CMOS • A Three-Stacked Switchable Hybrid-Shutter CMOS Image Sensor With 1.2-μm-Pitch 50-Mpixel Rolling Shutter and 2.4-μm-Pitch 12.5-Mpixel Global Shutter Modes for Mobile Applications • Sub-μA Always-on Drive Loop for 3-Axis MEMS Gyroscope • An Eye-Opening Arbiter PUF With Auto-Error Detection and PVT-Robust Masking Achieving a BER of 2e−8