some electronics

===== #analog

Охохо, Дмитрий Маленда @MALPOWER выдал шикарную статью-инструкцию по теме моделирования в ANSYS MAXWELL. ===== #power #ansys

PCI Express® Electrical Basics ===== #PCIe #basic #ABC

10 THINGS TO KNOW ABOUT PCIe ===== #PCIe #basic #ABC

Rapid Open Hardware Development (ROHD) Framework https://github.com/intel/rohd Yet another попытка ухода от низкого уровня HDL к чуть более высокоуровневым описаниям, причем довольно свежая (репозиторию и 2 недель нет). Что на этот раз: Intel, язык Dart, фреймворк для дизайна и верификации, амбиции построить opensource community вокруг. ROHD is not a new language, it is not a hardware description language (HDL), and it is not a version of High-Level Synthesis (HLS). ROHD can be classified as a generator framework. You can think of this project as an attempt to replace SystemVerilog and related build systems as the front-end methodology of choice in the industry.

One of ROHD's goals is to help grow an open-source community around reusable hardware designs and verification components.

Ну и фич целый вагон: ▫️Full power of the modern Dart language for hardware design and verification ▫️Makes validation collateral simpler to develop and debug. A future package (like UVM for ROHD) to help build testbenches is planned for release soon. ▫️Develop layers of abstraction within a hardware design, making it more flexible and powerful ▫️Easy IP integration and interfaces; using an IP is as easy as an import. Reduces tedious, redundant, and error prone aspects of integration ▫️Simple and fast build, free of complex build systems and EDA vendor tools ▫️Can use the excellent pub.dev package manager and all the packages it has to offer ▫️Built-in event-based fast simulator, with waveform dumper to .vcd file format ▫️Conversion of modules to equivalent, human-readable, structurally similar SystemVerilog for integration or downstream tool consumption ▫️Run-time dynamic module port definitions (numbers, names, widths, etc.) and internal module logic, including recursive module contents ▫️Simple, free, open source tool stack without any headaches from library dependencies, file ordering, elaboration/analysis options, +defines, etc. ▫️Excellent, simple, fast unit-testing framework ▫️Less verbose than alternatives (fewer lines of code) ▫️Enables higher quality development ▫️Replaces hacky perl/python scripting for automation with powerful native control of design generation ▫️Fewer bugs and lines of code means shorter development schedule ▫️Support for cosimulation with verilog modules and instantiation of verilog modules in generated SystemVerilog code ▫️Use modern IDEs like Visual Studio Code, with excellent static analysis, fast autocomplete, built-in debugger, linting, git integration, extensions, and much more ▫️Simulate with various abstraction levels of models from architectural, to functional, to cycle-accurate, to RTL levels in the same language and environment. Ну и естественно они не могли не пройтись по альтернативам в лице: SystemVerilog, Chisel, MyHDL, HLS, TL-Verilog, PyMTL, cocotb. #digital_design #verification #framework #dart #rtl

Handbooks & Technical Memoranda Architecture from ESA. ===== #engineering #ESA

80-ядерный процессор Ampere Altra на архитектуре Arm Neoverse N1. ADLINK сделала для него плату COM-HPC Altra, куда встают разнве версии процессоров (от 32 до 80 ядер). 64-битные ядра Arm v8.2 на частоте 2.8 ГГц, жрёт до 175 ватт, поддерживает 768 ГБ DD4 оперативки. Наружу 3 порта PCIe Gen4 x16, 4*10GbE и 1*1GbE.

CoolGaN™ транзисторы от Infineon ===== #power #GAN